Step 3.1: Configure Analog-to-Digital Converter (ADC) Peripheral Library (PLIB)
Configure ADC Peripheral
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Select the ADC Peripheral Library and configure it to sample and convert the light sensor input. The ADC is also configured to generate an interrupt (and thereby wake the CPU) when the ADC result is greater than a set Window Monitor Low Threshold value (3000 for this example).
- When the light sensor is not covered (light is falling on the sensor), the phototransistor is turned on. The ADC input is ~0 V and the ADC RESULT register is close to 0x000.
- When the light sensor is covered (light is not falling on the sensor), the phototransistor is turned off. The ADC input is ~3.3 V and the ADC RESULT register will be saturated (0xFFF).
- The ADC RESULT register is compared with the Window Lower Threshold (WINLT), which is set to 3000.
- When the light sensor is covered (ADC RESULT > WINLT), an ADC Window Monitor Interrupt is generated. This interrupt is used to bring the CPU out of Idle/Standby Sleep mode when you cover the light sensor.
a
Select Prescaler: Peripheral clock divided by 2 divides the ADC input clock with the configured pre-scaler value and provides more sampling time (CLKADC = 1 MHz/2 = 500 kHz).
b
Select Reference: VDDANA
c
Select Conversion Trigger: HW Event Trigger
d
Start Event Input: Enabled on Rising Edge
e
Select Positive Input: ADC AIN18 Pin (the light sensor is connected to AIN18 pin of ADC.)
f
Select Result Resolution: 12-bit result (ADC conversion value range from 0 to 4096.)
g
Open the Window Mode Configuration panel:
- Select Window Monitor mode: Result > WINLT. A Window Monitor Interrupt is generated when the ADC result is greater than the configured WINLT value.
- Window Upper Threshold: Sets the upper threshold of the window comparator. It is set to 0 as the ADC resolution is 12-bit.
- Window Lower Threshold: Sets the lower threshold of the window comparator. It is set to 3000. This means that the ADC Window Monitor Interrupt will be generated when the ADC result is greater than 3000. This value is decided based on the light sensor voltage when we cover the light sensor; it approximately generates 2.2 V. Hence threshold is set near to this voltage.
- Enable Window Monitor Interrupt: A Window Monitor Interrupt is generated when the ADC result is greater than the configured WINLT.
h
Open the Sleep Mode Configuration panel:
- Enable Run During Standby
- Enable On Demand Control
Configure ADC Pin
Configure ADC Clock for Low-Power
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Once the window is opened, scroll down to the ADC peripheral and select GCLK1 (1 MHz) as the source clock to generate the peripheral clock frequency.
The ADC peripheral clock is by default set to GCLK0. However, to benefit from SAM L21 clock tree, the ADC peripheral clock is fed by GCLK1 to run at 1 MHz. Running a slower clock on the ADC reduces the power consumption during Sleep mode.
This completes the configuration of the ADC PLIB. The ADC is configured to start conversion on a hardware event trigger and generate an interrupt if the converted value is higher than a defined WINLT value.
Step 3.2: Configure External Interrupt Controller (EIC) PLIB for Switch Button
Configure EIC Peripheral
Configure EIC Pin
4
Once the MCC Pin Settings window is opened, scroll-down to pin number 3 and configure this pin:
- Enable EIC_EXTINT2 on pin number 3:
- Pin ID: PA02
- Custom Name: SW0
- Function: EIC_EXTINT2
In the Peripheral Clock Configuration, EIC is by default connected to the GCLK0. However, the EIC clock configuration is set to run at 32 kHz using the OSCULP32K source clock directly, as defined in the Configuration Options of the EIC peripheral.
This completes the configuration of the EIC PLIB. The EIC is configured to produce an interrupt which will wake the device up from Sleep mode whenever the switch is pressed. This feature is used to measure the wakeup time from Sleep mode (Idle or Standby). The EIC is configured to run on the internal low power 32 kHz clock regardless of its configuration in the Peripheral Clock Configuration.
Step 3.3: Configure Event System (EVSYS) PLIB
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Configure the EVSYS channel 0 on the Event System Manager window:
- Set the Real-Time Clock Compare 0 (RTC_CMP_0) event as the event generator. The event is configured to appear asynchronously and to run in Standby mode with the on-demand feature enabled.
- Set the ADC Start of Conversion (ADC_START) as the event user.
Make sure that the status of the event and user (Event Status and User Ready) is green. If it is red, verify that the Event Output and Event Input are enabled in the respective PLIB configuration (RTC and ADC for this application example).
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