Description on PDEC (HALL mode) in SAME54
- In Hall mode, COUNT register, CC0 and CC1 are split into two parts (MSB and LSB registers). The current hall value is available in the COUNT LSB (2:0).
- MC0 and MC1 Interrupt Flag bit is set (INTFLAG.MC[x]), if COUNT MSB register matches with CC[x] MSB.
- OVF interrupt will rise on match of CC0 LSB register against COUNT LSB register, which contains current hall code.
- Velocity Interrupt (VLC) will rise on whenever Hall state (values) changes.
- The window counter is checked to be between CC0 [MSB] and CC1 [MSB] value and reset to 0 value. If an error is detected, the Window Error bit in Status register (STATUS.WINERR) is set.
- If there is any change in the direction of the hall pattern, the DIR interrupt flag becomes active.
- The COUNT MSB gives the count of the window counter which runs on the PDEC clock.
Step 2.1 - Configure PDEC Peripheral Library and PDEC Pins
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Select the MHC Pin Settings tab and sort the entries by Ports as shown:
Select the PDEC Hall pins as:
Enable PDEC Hall A pin (PDEC_QDI0) on PC16 (Pin #70)
Enable PDEC Hall B pin (PDEC_QDI1) on PC17 (Pin #71)
Enable PDEC Hall C pin (PDEC_QDI2) on PC18 (Pin #72)
These Hall pins details are available in Chapter 1, "PIM to MCU Mapping" of "ATSAME54 100-Pin Motor Control Plug-In Module Information Sheet".
This completes the configuration of the PDEC peripheral library. This application code will use the PDEC PLIB Application Peripheral Interfaces (APIs) to read Hall values from the Hall sensor.
Step 2.2 - Configure TCC0 Peripheral Library and TCC0 Pins
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As mentioned in Step 2.1, once TCC0 is successfully added, it will be listed under the Active Components tab.
When a module is added to the project graph, MHC automatically enables the clock to the module. The default TCC0 source is Generic Clock Controller 1 (GCLK1). You can verify the clock source using Clock Configuration view.
Step 2.3 - Configure ADC0 Peripheral Library
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As mentioned in Step 2.1, ADC0 is successfully added and it will be listed under Active Components tab.
When a module is added to the project graph, MHC automatically enables the clock to the module. The default ADC0 source is Generic Clock Controller 1 (GCLK1). You can verify the clock source using Clock Configuration view.
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Go back to the project graph and configure the ADC0 PLIB.
ADC AIN6 (Channel 6) is selected here because the potentiometer signal of MLCV2 board is connected to this specific ADC channel 6. This information is available in Chapter 1, "PIM to MCU Mapping" of "ATSAME54 100-Pin Motor Control Plug-In Module Information Sheet".
This completes the configuration of ADC0 peripheral library. This application code will use the ADC0 PLIB Application Peripheral Interfaces (APIs) to read the output voltage of the potentiometer to determine the speed.
Step 2.4 - Configure TC0 and TC1 Instances in TC Peripheral Library
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As mentioned in Step 2.1, once TC0 is successfully added, it will be listed under the Active Components tab.
When a module is added to the project graph, MHC automatically enables the clock to the module. The default TC0 clock source is Generic Clock Controller 1 (GCLK1).
From the default clock GCLK1, change the clock source of TC0 to GCLK3 (8 MHz) as shown:
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Since TC0 and TC1 share the same clock bus, TC1 is assigned to the same clock source as theTC0 configuration. TC1 clock source is GCLK3 (8 MHz), the same as TC0.
Step 2.5- Configure Event System Peripheral Library
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Event System (EVSYS) is added to the Project Graph by default.
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Add Event channel and User by clicking the Add Channel button and the Add User button.
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