Voice Recorder Tutorial: Step 2

Step 2: Configure Audio CODEC, I2C, and I2S Drivers

Step 2.1: Configure Audio CODEC (AK4953)

Click on the Options tab in the main window of MPLAB Harmony Configurator (MHC).
Expand the Harmony Framework Configuration > Drivers > CODEC selection tree.

Remember, if you ever lose the MHC Tool, you can find it here:
Tools > Embedded > MPLAB Harmony Configurator.

Check the Use Codec AK 4953? box.

A default value for Volume is specified. You can change the value depending on your requirements.

Do not check Specify MCLK value. A default value of 256 for MCLK is selected under I2S driver configuration options MCLK Sampling rate Multiplier.

Only one client of the CODEC driver needs to be opened, therefore, retain the Number of AK4953 Driver Clients value to "1".

The AK4953 Driver supports only one instance of the AK4953 CODEC module. AK4953 driver is a single instance driver. Therefore, the default instance of Codec AK4953 Driver Instance 0 is selected.

Select the I2S driver (used for data interface) instance as DRV_I2S_INDEX_0. The AK4953 driver uses the I2S interface for the Audio data transfer to/from the PIC32 microcontroller. The PIC32MZ2048EFH144 device supports multiple instances of I2S peripheral modules. You need to specify which instance (Instance 0 in this case) of the I2S peripheral is used for this driver.

Select the I2C driver (used for control interface) instance as DRV_I2C_INDEX_0 or 0. The AK4953 driver uses I2C interface for the Audio control transfers to/from the PIC32 microcontroller. The control transfers exchanges commands to/from the AK4953 CODEC to configure and/or read the initialized/existing configuration. PIC32MZ2048EFH144 device supports multiple instances of I2C modules. An instance (Instance 0) for Audio control communication is selected.

The CODEC devices need a fine clock source to generate accurate audio sampling rates. The clock source (MCLK from the CODEC device’s perspective) can be generated internally by the CODEC device.

PIC32 devices have a flexible reference clock output. The reference clock output module (REFCLKO) can be used to generate the fractional clock that can be used by audio CODEC/DACs to accommodate various sample rates.

The MCLK value represents the multiplier to the sampling frequency (LRCK) which produces the value for the master/reference clock (MCLK/REFCLOCK) to the CODEC. This value should be one of the fs values supported by the CODEC for various sampling rates.

For example: For 256 fs, The MCLK value of 256 for a sampling rate of 48000 Hz would generate an MCLK/REFCLOCK of 12288000 Hz. By default, an MCLK value of 256 is selected. This is also shown in the default I2S driver configuration options MCLK Sampling rate Multiplier. If you intend to select a different MCLK value, check Specify MCLK value. It shows the following selectable options: 128, 192, 256, 384, 512, 768, and 1152.

Step 2.2: Configure I2C Driver for CODEC

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In AK4953 CODEC driver configurations, I2C is selected as the control interface medium (expand Harmony Framework Configuration > Drivers > CODEC > Use Codec AK4953? selection tree to see this). Next, configure the I2C interface driver.

Expand the Harmony Framework Configuration > Drivers > I2C selection tree.

The Use I2C Driver? is checked by default. MHC selected this for you because the AK4953 CODEC driver uses the I2C driver.

Select Dynamic for the Driver Implementation. A Dynamic I2C driver implementation will allow the implementation to be used for another instance of the I2C module in this lab (needed for the touch screen).

Check the Interrupt mode option. This allows I2C data completion events to be detected asynchronously, without the need for polling for the transfer to complete. This is necessary because, by the end of the lab, you will add several Harmony drivers, system services, and middleware libraries. All these Harmony modules have to cooperatively run without blocking the processor.

Keep the Number of I2C Driver Clients and Number of I2C Driver Instances set to "1" since at this time I2C is only used to interface with the AK4953 CODEC. You will increase this number in a following lab to enable this driver to support multiple I2C interfaces.

Check Include Force Write I2C Function. This will include an API that sends data to the slave even if the slave NACKs data. This is needed by the AK4953 CODEC since it NACKs I2C data during the initialization sequence.

Under I2C Driver Instance 0, check the Use Bit Bang I2C Implementation? option.

Select I2C_ID_2 as I2C Module ID. I2C module instance 2 is interfaced to the AK4953 CODEC’s control interface.

I2C_ID_2 refers to the PIC32 I²C2 peripheral (using pins SCL2 & SDA2). These pins are connected to the AK4953 audio CODEC on the MEB II board.

Retain the default value DRV_I2C_MODE_MASTER as Operation Mode. PIC32 I2C module 2 will act as the master, and the AK4953 CODEC module control interface (I2C) will act as the slave.

Retain the Bit Bang Timer Source as DRV_TMR_INDEX_9. Timer module 9 will be used to clock the I2C bit-bang state machine. Based on the selected baud rate (I2C CLOCK FREQUENCY (HZ)), the I2C driver will configure the timer to generate interrupts at appropriate intervals. You can select any Timer module as the Bit Bang Timer Source, as long as the timer source is not used by another module.

Change the I2C CLOCK FREQUENCY (HZ) to 25 KHz.

Change the I2C Interrupt Priority to INT_PRIORITY_LEVEL_5, and the I2C Interrupt Sub-priority to INT_SUBPRIORITY_LEVEL0. For I2C configured in bit bang mode, these interrupt priorities indicate the interrupt priority of the timer module (DRV_TMR_INDEX_9).

Step 2.3: Verify the I/O Pins Used by I2C Module

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Step 2.4: Configure I2S Driver for CODEC

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In AK4953 CODEC driver configurations, "I2S" is selected as the Audio data interface medium. Next, configure the I2S interface driver.
Expand the Harmony Framework Configuration > Drivers > I2S selection tree.

The Use I2S Driver? is checked by default. This is done since the AK4953 CODEC driver uses the I2S driver.

Expand the Use I2S Driver? option.

Dynamic is selected (and greyed out) for Driver Implementation by default. The I2S driver does not support static implementation yet.

Verify the DMA has been correctly configured for you. Verify the DMA Mode box is checked, then expand this selection tree.

Verify the following boxes are checked:

Transmit DMA Support
- Transfers Audio Data from memory to I2S buffer.
Receive DMA Support
- Receives Audio Data from I2S buffer to memory.
Enable DMA Channel Interrupts?
- Allows DMA transfer completion notification.

Retain Stop in Idle Mode as it is.

Change the Sampling Rate to 16000. This is the sampling rate you are supporting for loopback and recording of audio data.

Retain default value of 256 for MCLK Sampling rate Multiplier. The AK4953 CODEC supports 256fs with 16000 Hz sampling rate for generating the REFCLOCK.

Retain default value of 4 for Master Clock/Bit Clock ratio.
For sampling rate 16000 Hz and MCLK Sampling rate multiplier value of 256, The Mater Clock (MCLK) or Reference clock (REFCLOCK) = 256 * 16,000 = 4,096,000 Hz. The common Bit Clock that can be generated for the given combination of MCLK and Sampling rate would be REFCLOCK/1, REFCLOCK/2, REFCLOCK/4 or REFCLOCK/8.
For Example: AK4953 CODEC supports bit clock (BCLK) value as either 32fs or 64fs. For 16000 Hz sampling rate, the Bit clock (BCLK) would be 64 * 16000 = 1,024,000 Hz. Therefore the MCLK/BCLK ratio is 4,096,000/1,024,000 = 4.

Retain default value of 1 set for Number of I2S Driver Clients and Number of I2S Driver Instances. The I2S interface is used only for Audio playback, therefore one instance of I2S driver and its client is sufficient.

Under I2S Driver Instance 0, retain SPI_ID_1 as I2S Module ID. The PIC32's SPI/I²S1 peripheral (PIC32 pins: SCK1, SDI1, SDO1, /SS1) is interfaced to the AK4953 CODEC’s data lines.

Retain default value of Usage Mode as DRV_I2S_MODE_MASTER. It indicates whether the I2S instance will act as a Master or Slave. In Master mode, PIC32 generates the BCLK to the Slave. In Slave mode, PIC32 receives Bit Clock (BCLK) from the I2S Master. In the interface to AK4953 CODEC, PIC32 I2S will act as a Master and hence, generates the BCLK.

Use the Reference Clock (198MHz) to drive the SPI baud rate generator. For the Baud Clock, select SPI_BAUD_RATE_MCLK_CLOCK. The SPI Baud Rate Generator can be driven by Peripheral Bus Clock #2 (PBCLK) or Reference Clock 1 (MCLK).

Retain default value of Clock Mode as
DRV_I2S_CLOCK_MODE_IDLE_HIGH_EDGE_FALL. The default polarity for I2S protocol.

Change Audio Communication Width to
SPI_AUDIO_COMMUNICATION_16DATA_16FIFO_32CHANNEL. In the scope of this lab CD quality, audio playback is supported. Therefore, setting 16 bit audio data per channel, 32 bit channel width.

Retain default value of Audio Mode as SPI_AUDIO_TRANSMIT_STEREO. The lab supports stereo Audio Playback.

Retain default value of Input Sample Phase Selection as SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE. The default phase for I2S protocol.

Retain default value of Audio Protocol Mode as DRV_I2S_AUDIO_I2S. I2S protocol interface mode is chosen as it is supported by AK4953 CODEC.

Change Queue Size Transmit to 8 This will allow queuing of up to 8 audio transmit buffer objects at a time.

Set Queue Size Receive to 16. This will allow queuing of up to 16 audio receive buffer objects at a time.

Retain Transmit DMA Channel Instance as 0 DMA Channel Instance 0 is used for Audio data transfer.

Change Receive DMA System Channel Instance to 1. You are using DMA Channel Instance 1 for Audio data receive.

Retain default value of SYS_MODULE_POWER_RUN_FULL for Power State. You want to run the I2S module in normal power mode.

Step 2.5: Configure CODEC Input Clock

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The PIC32 acts as I2S Master to the AK4953 CODEC. It needs to provide its "Reference Clock Generator Output 1" signal (REFCLKO1) to the CODEC's "External Master Clock Input" (MCKI) in addition to the Bit clock (BCLK).

Expand the Harmony Framework Configuration > Options > System Services > Clock selection tree.

Expand Use Clock System Service?.

Click Execute on Launch Clock Configurator.

Locate the Reference Clock block. By default the Reference Clock #1 tab is selected. The Reference Clock #1 enables configuring the reference clock to SPI/I2S, PPS.

Check ON box. This enables the reference clock circuitry.

Select SPLL as ROSEL1. The System PLL is used as the source clock for generating the reference clock.

Click the Auto-Calculate button to generate the Reference Clock #1. It opens up a window Reference Clock Divisor and Trim Auto Calculator.

Verify that the Reference Clock Divisor and Trim Auto Calculator show the desired Reference Clock and Sampling values to be generated. The values are generated from the MCLK multiplier and sampling rate specified in CODEC/I2S driver configuration.

Select the radio button Target I2S Input Frequency and click Apply button. The Target I2S Input Frequency is the reference clock input to the AK4953 CODEC.

If Target I2S Input Frequency is shown as 0, deselect and re-configure the I2S driver as explained above and come back to this step.
This is a known issue and will be fixed in subsequent Harmony releases.
Alternatively, for generating 4,096,000 Hz frequency for REFCLKO1 (for 16 kHz sampling rate), you may manually enter the value 87 for ROTRIM1(M) and a value of 24 for RODIV1(N) as shown below.

Check the OE box to enable the Reference Clock #1 output.

It is important to note that a reference clock of 4,096,000 Hz cannot be accurately generated from a system clock of 200 MHz. It is for this reason that the system clock is configured to 198 MHz, during the oscillator settings step.