PIC32MX CPU Overview

The MIPS32® M4K® core implements the MIPS32 Release 2 Architecture in a five-stage pipeline. It includes the MIPS16e™ Application-Specific Extension (ASE), which improves code density through the use of 16-bit encodings of MIPS32 instructions plus some MIPS16e-specific instructions.

ASE: An application-specific extension to the MIPS® architecture. These are optional extensions defined in add-ons to the MIPS32/MIPS64 base architecture.
More information on MIPS ASEs is provided by MIPS.

The Memory Management Unit (MMU) consists of a simple, Fixed Mapping Translation (FMT) mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer (TLB) based MMU.

The core includes a Multiply/Divide Unit (MDU) that implements single cycle 32x16-bit MAC instructions or two-cycle 32x32-bit, which enable DSP algorithms to be performed efficiently.

The following key features are available on PIC®32-based MCUs on this core:

  • Up to 1.5 DMIPS/MHz of performance
  • Programmable prefetch cache memory to enhance execution from Flash memory (external to the core)
  • 16-bit Instruction mode (MIPS16e™) for compact code
  • Vectored interrupt controller with up to 96 interrupt sources
  • Programmable user and kernel modes of operation
  • Atomic bit manipulations on peripheral registers (Single cycle)
  • MDU with a maximum issue rate of one 32 x 16 multiply per clock
  • High-speed Microchip ICD port with hardware-based non-intrusive data monitoring and application data streaming functions
  • EJTAG debug port allows extensive third-party debug, programming and test tools support
  • Instruction controlled power management modes
  • Five-stage pipelined instruction execution
  • Internal code protection to help protect intellectual property
  • Additional "shadow" GPR register set for reduced interrupt latency

CPU Core Documentation:
The following documents are available from MIPS:

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