L1 Cache

A Central Processing Unit (CPU) cache is a separate small block of memory used to compensate for the slower access time of the main memory. A cache described as a Level 1 (L1) cache uses memory that is as fast as the CPU, so as long as the CPU is accessing the cache, it will never have to wait for instruction or data. Level 2 and Level 3 caches are used in conjunction with a Level 1 cache and have memory whose access times are greater than the CPU, but are less than main memory.


The PIC32MZ family uses a L1 cache only. The L1 cache is divided into two parts: an instruction cache and a data cache. The use of the cache is critical to achieving maximum performance from the PIC32MZ family. Memory access to and from the cache always occurs in a single clock cycle. Accessing the main memory could take three or more cycles.

"Single cycle" refers to one instruction cycle, which is one PBCLK7 clock.

Application Note "AN1600" covers detailed use of L1 cache memory on PIC32MZ devices.

Also, there is a PIC32MZ cache tutorial that goes into further details on the configuration/use of the L1 cache.

By default, MPLAB® XC32 start-up code enables the cache and configures it in write-back with write allocation mode.

This policy is the easiest for the hardware to implement and consumes the least system bus resources and power. However, it is the least useful for keeping shared data coherent. Combining this cache policy with using uncached (KSEG1) memory for shared data is the simplest cache management approach, and is recommended for getting your project up and running.

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.