Memory Organization: Overview

The PIC32MZ family of microcontrollers provides 4 GB of unified, virtual memory address space. There are several features of this memory system that are distinct, as compared to other PIC® Microcontrollers (MCUs):

  • Unified Address Space: Instructions and data share the same memory space
    • C-Friendly - no need for special rom or psv pointer declarations.

Although the address space is unified, PIC32MZ MCUs contain multiple bus interfaces to allow concurrent instruction and data access, thus, implementing a Harvard style hardware bus architecture, similar to existing 8-/16-bit PIC® MCUs.

  • Virtual Memory Addressing

All MIPS®-based CPUs implement 2 address spaces: a virtual address space, consisting of all the addresses that can be used in a program and a physical address space, consisting of all the addresses that can be sent out on the address bus. Virtual addresses are mapped (translated) to physical addresses by the memory management unit (MMU).

  • Multi-Layer System Bus

To Summarize: Addresses in the PIC32MZ are:

  • Issued as virtual addresses by the MIPS core, then
  • Mapped into physical addresses by the MIPS memory-management-unit (MMU), then
  • Mapped into a bus address via the multi-layer system bus, and finally
  • Used to select the appropriate peripheral or location in RAM

Other key features of PIC32MZ memory organization include the following:

  • 32-bit native data width
  • MMU with fixed mapping allows for securely configurable memory and peripheral access control permissions
  • Bus arbitration scheme is implemented using a least recently serviced (LRS) priority to provide a Quality of Service (QOS) for the CPU, general purpose DMA, and peripherals with dedicated DMA
  • Dual Flash panels allow for live updates of program memory
  • Separate dual boot Flash memory allows updates of boot code
  • Dual RAM banks can be used to avoid bus arbitration when using DMA
  • External serial and or parallel memory can be mapped into virtual memory space for data access or code execution using the Serial Quad Interface (SQI) or External Bus Interface (EBI)
  • Cacheable and non-cacheable address regions

Please refer to Section 48. Memory Organization and Permissions (DS60001214) for detailed coverage on the memory organization and configuration.

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.