Parallel trace is possible using a device 8-pin I/O port and the emulator logic probes. This provides greater trace speed and data quantity, but limits emulator-to-target distance by the length of the logic probes. The figure below shows these additional connections.
Figure: Parallel Trace Connections
For this trace configuration, seven (7) lines of data and one (1) line for clock are transmitted. PORTx must be a port with 8 pins that has all 8 pins available for trace. The port does not have to be one physical port but can be made up of pins from more than one port. The port pins must not be multiplexed with the currently-used PGC and PGD pins.
For allowable PORTx configurations:
- Right-click on your project in the Projects window and select "Properties".
- In the Project Properties window, click on the “REAL ICE” category
- Select the “Trace and Profiling” option category from the drop down list.
- Under “Data Collection Selection”, select the trace that is supported for your device, e.g., “User Instrumented Trace”.
- Under “Communications Medium”, select “I/O Port”.
- Under “I/O Port Selection”, select your port configuration from the list.
A basic configuration is shown in the following table.
Table: I/O Port Trace Connection Example
| PORTx pin | Logic Probe pin(1) | Content |
|---|---|---|
| 0 | EXT0 | Data |
| 1 | EXT1 | Data |
| 2 | EXT2 | Data |
| 3 | EXT3 | Data |
| 4 | EXT4 | Data |
| 5 | EXT5 | Data |
| 6 | EXT6 | Data |
| 7 | EXT7(2) | Clock |
Note 1: For pin descriptions, see “Logic Probe/External Trigger Interface” under Emulator Pod Hardware.
Note 2: Use a 10 kΩ pull-down resistor for noise reduction.
Do not use pull-up or pull-down resistors, capacitors or diodes on port pins, except as specified.
For more on this type of trace, see Types of Instrumented Trace.